The present invention lies in the field of semiconductor devices and methods for fabricating semiconductor devices, especially MOS and bipolar devices. More particularly, the present invention lies in the field of methods for forming a planarized surface over a metal interconnect layer.
In modern integrated circuits, multiple metal layers are used for wiring (or "interconnecting") the active transistors to form useful functional circuits. Metal layers are deposited by physical or chemical vapor deposition (PVD or CVD) methods and then etched using a photolithographic mask to form patterns of metal strips which act as wires. In a typical circuit, these strips may be as narrow as the metal layer is thick (e.g., less than 1 .mu.m), and the gaps between metal strips may be equally narrow. After the metal layer has been etched, the surface of the integrated circuit is not planar, and, in fact, contains many steps as high as the metal thickness and separated by comparable distances.
In order to continue the fabrication process, the surface containing the metal strips must be covered by a layer of suitable dielectric material to insulate the metal interconnect strips from the next layer of metal. Holes or vias are then cut in the dielectric layer where vertical interconnections are desired between the metal layers. Unfortunately, present dielectric deposition techniques, such as CVD or plasma enhanced CVD (PECVD), have difficulty covering steps conformally and often do not adequately fill the narrow slots between closely spaced metal lines. Thus, undesirable voids may be left in these slots. Further, even if no voids are left, the upper surface of the deposited dielectric will have steps of height comparable to that of the metal interconnect runners. These height variations will make it difficult to obtain consistent focus and complete exposure in subsequent photolithography steps. In addition, the ridges and valleys on the dielectric surface are difficult to cover with metal for the next interconnect layer.
To address these problems, the current art has developed several planarization techniques to smooth the surface of dielectric layers over patterned metal layers. For example, spin-on-glass (SOG) or (sol-gel technology) is one widely-used method used to fill narrow gaps without leaving voids. In this method, a thin dielectric layer is deposited by CVD and then a liquid material (which forms the glass) is spun on the surface. This liquid fills the narrow gaps and converts sharp steps to more gently sloping ones. After it hardens, the SOG is often partially etched back to minimize the amount of SOG left on the wafer, and then covered by a second CVD glass layer. Unfortunately, SOG materials are porous and tend to absorb water. In addition, they do not produce a planar wafer surface, having height variations as great as the thickness of the underlying metal layer. This height differential builds up as each metal layer is added, causing increasing difficulty in lithography.
Another previous method involves steps of first depositing a dielectric layer over the metal lines followed by steps of spinning an organic layer such as photoresist over the rough dielectric layer and etching back the composite layer using an etch process which attacks the dielectric and the organic at the same rate. This method requires a dielectric deposition method capable of filling the gaps between metal lines, as no organic can be left on the wafer. Unfortunately, this method also leaves steps on the surface similar to those left by a SOG process.
Still another method uses chemical-mechanical polishing (CMP) to planarize the dielectric layer over metal strips. This technique is discussed in detail in the following U.S. patent applications which are incorporated herein by reference for all purposes: U.S. Ser. No. 07/874,675 and U.S. Ser. No. 07/874,493. CMP is particularly desirable because it provides "global planarization." In other words, the leveling lengths provided by CMP are so great that even widely spaced steps (i.e. steps that are approximately 1 mm apart) on typical integrated circuits are eliminated. However, applying CMP to a dielectric layer over metal strips has certain disadvantages. First, polishing dielectrics such as silicon dioxide used as insulators in integrated circuits is relatively slow and expensive. Second, in cases where the underlying metal lines are made of a soft metal such as aluminum, CMP can damage the metal. This second problem could be alleviated if effective polish stopping materials capable of protecting the metal lines from attack were known. A thin layer of such materials could be used to coat the interconnect lines before the main dielectric layer was formed. Unfortunately, no such materials are known that also offer high resistance to a dielectric CVD process and are otherwise compatible with integrated circuit processing. Thus, the CMP step must be carefully controlled to ensure that the metal interconnects are not exposed. This requires that sufficient margin must be built into the fabrication process to accommodate this lack of control. In some instances, this can be accomplished by increasing the thickness of the dielectric layer.
Thus, it is seen that improvements are still needed in the fabrication procedures for interconnect layers in various integrated circuit devices.